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| Technical Data Sheet Photo link Light Receiver Unit PLR135 Features 1. High PD sensitivity optimized for red light 2. Data : NRZ signal 3. Low power consumption for extended battery life 4. Built-in threshold control for improved noise Margin 5. Good ESD protection: up to 8KV 6. Pb Free 7. Receiver sensitivity: up to -27dBm (Min. for 16Mbps) up to -21dBm (Min. for 25Mbps 8. The product itself will remain within RoHS compliant version. Descriptions The optical receiver is packaged with custom optic data link interface, integrated on a proprietary CMOS PDIC process. The unit functions by converting optical signals into electric ones. The unit is operated at 2.4 ~ 5.5 V and the signal output interface is TTL compatible with high performance at low power consumption. Applications 1. Digital Optical Data-Link 2. Dolby AC-3 Digital Audio Interface Everlight Electronics Co., Ltd. Device NO.: DPL-135-001 http://www.everlight.com Prepared date: 07-25-2005 Rev 2 Page: 1 of 8 Prepared By: Chin-Chia Hsu PLR135 Package Dimensions Pin Function 1 : Vout 2 : GND 3 : Vcc 3 2 1 Notes: 1.All dimensions are in mm. 2.General Tolerance: Pin length tolerance is 0.25 mm others are 0.10 mm Everlight Electronics Co., Ltd. Device NO.: DPL-135-001 http://www.everlight.com Prepared date: 07-25-2005 Rev 2 Page: 2 of 8 Prepared By: Chin-Chia Hsu PLR135 Absolute Maximum Ratings( Ta = 25 C) Parameter Supply Voltage Output Voltage Storage Temperature Operating Temperature Soldering Temperature * Soldering time 10 s. Symbol Vcc Vout Tstg Topr Tsol Rating -0.5 ~ +5.5 Vcc +0.3 -40 to 85 -20 to 70 260* Unit V V C C C Electro-Optical Characteristics(Ta=-20~70,Vcc=3V) Parameter Power supply voltage Peak sensitivity wavelength Maximum receiver power Minimum receiver power Dissipation current High level output voltage Low level output voltage Rise time Fall time Propagation delay Low to High Propagation delay High to Low Pulse Width Distortion Jitter Transfer rate Symbol Vcc p Pc,max Pc,min Icc VOH VOL tr tf tPLH tPHL tw tj T Conditions Refer to Fig.1 Refer to Fig.1 Refer to Fig.2 Refer to Fig.3 Refer to Fig.3 Refer to Fig.3 Refer to Fig.3 Refer to Fig.3 Refer to Fig.3 Refer to Fig.3 Refer to Fig.3, Pc=-14dBm Refer to Fig.3, Pc=-27dBm MIN. TYP. MAX. Unit 2.40 -27 2.1 3.00 650 4 2.5 0.2 10 10 -25 0.1 1 5 5.50 -14 12 0.4 20 20 120 120 +25 15 20 16 V nm dBm dBm mA V V ns ns ns ns ns ns ns Mb/s NRZ signal Everlight Electronics Co., Ltd. Device NO.: DPL-135-001 http://www.everlight.com Prepared date: 07-25-2005 Rev 2 Page: 3 of 8 Prepared By: Chin-Chia Hsu PLR135 Measuring Method *Fig.1 Measuring Method of Maximum and Minimum Input Power that Receiver Unit Need Control Circuit Standard plastic optic fiber cable Transmitter PLR135 Receiver Unit Optical Power Meter *Fig.2 Measuring Method of Dissipation Current Standard plastic optic fiber cable Standard Transmitter Unit Vin Vcc GND PLR135 Receiver Unit Vcc GND Vout 47uH Signal Input 16 Mbps NRZ "0101" successive signal input A 0.1uF 3V Everlight Electronics Co., Ltd. Device NO.: DPL-135-001 http://www.everlight.com Prepared date: 07-25-2005 Rev 2 Page: 4 of 8 Prepared By: Chin-Chia Hsu PLR135 *Fig.3 Measuring Method of Output Voltage, Pulse and Jitter Standard plastic optic fiber cable Standard Transmitter Unit Vin Vcc GND PLR135 Receiver Unit Vcc GND Vout 47uH Signal Input 16 Mbps NRZ "0101" successive signal input TPLH TPHL 0.1uF A 3V CH1 Input Output tj1 50% CH2 50% tj2 tw = TPHL-TPLH Application Circuit (1) General application circuit for Vcc=3V (2) General application circuit for Vcc=5V Receiver Unit Receiver Unit C1 C1 C2 Vcc L2 GND Vout C1:0.1uF Vcc L2 GND Vout C1:0.1uF C2:30pF (Suggestion) L2:47uH 3V L2:47uH 5V Note: For having good coupling, the C1,C2 capacitor must be placed within 7mm Everlight Electronics Co., Ltd. Device NO.: DPL-135-001 http://www.everlight.com Prepared date: 07-25-2005 Rev 2 Page: 5 of 8 Prepared By: Chin-Chia Hsu PLR135 Typical Electro-Optical Characteristics Curves *Fig.4 Power supply voltage vs. Minimum receiver power Operating Transfer Rate 16Mbps 25Mbps *Fig.5 Transfer rate vs. Minimum receiver power -30 -32 Operating Voltage Vcc=3.3V Optical Input Sensitivity (dBm) Optical Input Sensitivity (dBm) -30 -28 -26 -24 -22 -20 -18 -28 -26 -24 -22 -20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 5 10 15 20 25 Operating Voltage (V) Transfer Rate (Mbps) Note: Before using the PLR135 device, please confirm the minimum sensitivity at different operating voltage and transmission rate. Everlight Electronics Co., Ltd. Device NO.: DPL-135-001 http://www.everlight.com Prepared date: 07-25-2005 Rev 2 Page: 6 of 8 Prepared By: Chin-Chia Hsu PLR135 RELIABILITY TEST ITEMS No. Item Test Condition 260C5C Test Hour/Cycle 1 Soldering Heat 10 seconds 1000hrs 1000hrs 1000hrs Sample Size (Piece) 22 22 22 22 Number (n) Failure (c) n=22, c=0 n=22, c=0 n=22, c=0 n=22, c=0 2 High Temp. Storage Ta=100C 3 Low Temp. Storage 4 High Temp. & Humid. Test 5 Temperature Cycle (30min) (5min) (30min) -10C ~~~~ 6 Thermal Shock (5min) (10sec) (5min) 100C Ta=85C, RH=85% -55C ~~~~ 85C Ta=-55C 300cycle 22 n=22, c=0 300cycle 22 n=22, c=0 7 DC Operating Life Vcc=3V, Ta=25C 1000hrs 22 n=22, c=0 Everlight Electronics Co., Ltd. Device NO.: DPL-135-001 http://www.everlight.com Prepared date: 07-25-2005 Rev 2 Page: 7 of 8 Prepared By: Chin-Chia Hsu PLR135 Application Notes: PLR135 Series PCB layout for motherboard integration To achieve better jitter and low input optical power performances, several PCB layout guidelines must be followed. These guidelines ensure the most reliable PLR135 POF performance for the motherboard integration. Failed to implement these PCB guidelines may affect the PLR135 jitter and low input power performances. 1. Careful decoupling of the power supplies is very important. Place a 0.1uf surface mount (size 805 or smaller) capacitor as close as (less than 2cm) to the POF Vdd and Gnd leads. The 0.1uf act as a low impedance path to ground for any stray high frequency transient noises. 2. To reduce the digital noises form the digital IC on the motherboard, the planar capacitance formed by an isolated Vcc and Gnd planes is critical. The POF device must be mounted directly on these two planes to reduce the lead parasitic inductance. 3. The isolated Vdd and Gnd planes must be connected to the main Vcc and Gnd (digital) planes at a single point using ferrite beads. The beads are used to block the high frequency noises from the digital planes while still allowing the DC connections between the planes EVERLIGHT ELECTRONICS CO., LTD. Office: No 25, Lane 76, Sec 3, Chung Yang Rd, Tucheng, Taipei 236, Taiwan, R.O.C Tel: 886-2-2267-2000, 2267-9936 Fax: 886-2267-6244, 2267-6189, 2267-6306 http://www.everlight.com Everlight Electronics Co., Ltd. Device NO.: DPL-135-001 http://www.everlight.com Prepared date: 07-25-2005 Rev 2 Page: 8 of 8 Prepared By: Chin-Chia Hsu |
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